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June 19, 2011 / Chris Merck

A Simple but Powerful Makefile Template

Want to build several executables in the same directory, each of which uses several .c files, and may have common dependancies linked in? Then this makefile is for you:

# Makefile for swdsp project

CC= gcc
SWDSP_LIBS = -lm -lpthread -ljack

EXES= swdsp-example #vsynth

all: $(EXES)

swdsp.o: swdsp.h swdsp.c
	$(CC) $(CFLAGS) -c swdsp.c

swdsp-example: swdsp-example.c swdsp.o
	$(CC) $(CFLAGS) $(SWDSP_LIBS) -o swdsp-example swdsp-example.c swdsp.o

#vsynth: vsynth.c swdsp.o
#	$(CC) $(CFLAGS) $(SWDSP_LIBS) -o vsynth vsynth.c swdsp.o

	rm -f $(EXES) *.o

This builds a program called “swdsp-example”, which depends on the file “swdsp.c”. There is also a project called “vsynth”, but it is commented-out here.

You will need to change it to fit your needs, but the basic philosophy is helpful, imo.

Warning: The indenting is done with tabs. Failure to do so will result in great pain.


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